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Fault Tolerant VLSI Design Using Error Correcting Codes

Report Number: RADC-TR-88-321
Author(s): Hartmann, C. R. P., P. K. Lala, A. M. Ali, S. Ganguly & G. S. Visweswaran
Corporate Author: Syracuse University
Laboratory: Rome Air Development Center
Date of Publication: 1989-02
Pages: 67
Contract: F30602-81-C-0169
Project: 2338
Task: 233801
AD Number: ADA208337

Abstract:
Very Large-Scale Integration (VLSI) provides the opportunity to design fault tolerant, self-checking circuits with on-chip, concurrent error correction. This study determines the applicability of a variety of error-detecting, error-correcting codes (EDAC) in high speed digital data processors and buses. In considering both microcircuit faults and bus faults, some of the codes examined are: Berger, repetition, parity, residue, and Modified Reflected Binary codes. The report describes the improvement in fault tolerance obtained as a result of implementing these EDAC schemes and the associated penalties in circuit area.

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